Semiconductor devices, whether they are ICs, optical devices, sensors or discrete devices, are complex and hard to reverse engineer. Generally, it is not possible simply to look at the device and discern how it works – at least not with the naked eye. When considering patent protection for innovations in the sector, practitioners must therefore give careful consideration as to how infringement by competitors might be detected. Such considerations guide decisions on the suitability of patent protection, and carry through to the patent drafting process and prosecution strategy.
Under European patent practice, a process claim includes protection for a product of that process. However, to prove infringement, it will likely be necessary to gather evidence from the product alone – with access to competitors’ manufacturing facilities not generally being freely given. For this reason, semiconductor fabrication and packaging methods are best defined using features that are detectable in the end product. Processes such as isotropic or anisotropic etching or deposition steps using different precursors may leave detectable features. On the other hand, a masking layer itself will likely be entirely absent from a final product. So, focusing patent claims on detectable process steps is important. What sets a well-crafted patent application apart though is taking the time to explain how the use of the steps can be discovered from the product. What is detectable in the final product, and how might it be detected? Is a certain structural feature only currently achievable using the claimed method, and, if so, why? Including these details in a patent application can significantly strengthen the patentee’s position when it comes to proving infringement.
Inventions relating to compound semiconductors might be characterized by alloys having very specific constituent ratios for targeting particular applications. A robust patent claim for such an invention might focus on a careful definition of the selected ratios that achieve the requisite advantages. Detecting infringement of such a patent claim might be achieved by looking at macroscopic properties, e.g. characteristics of a device’s photovoltaic sensitivity or emission spectra. If so, then a well drafted patent application should include a description of the relevant characteristics that can be detected. Setting out comparative characteristics that might be observed in devices not incorporating the claimed invention can also be invaluable. However, if macroscopic effects may not be decisive, then an explanation of other material properties allowing identification of the claimed alloy might be necessary. In any event, establishing in the patent application how use of the claimed alloy may be proved, rather than just thinking of how to support inventiveness, makes for a more robust patent.
Microchips can be analyzed using X-ray tomography or by carefully stripping the chip down and inspecting it layer by layer using electron microscopy. These techniques can identify structures on the chip, such as vias, interconnects, contacts, wells and so on. Despite current technology having brought these structures down to the scale of a few nanometers, careful imaging can identify relative dimensions, shapes and arrangements of individual features on a chip. Moreover, images over the extent of the chip can allow the layout of components on the chip to be identified, along with relevant arrangements of the components. Patent claims defining precise structures or layouts can therefore be compared to real products, albeit at considerable expense and cost. Functionality is perhaps trickier, as expert analysis is required to infer with any certainty that specific structures or layouts operate in a particular way. Therein lies a difficulty, because broad patent claims often use functional wording. A skilled practitioner can address this by careful choice of claim language, typically tying together structure and function. However, the best patents foreshadow how infringement might be detected, and ensure the specification contains guidance on what relevant chip level structures and layouts might look like, and how they might vary. Claim language that defines a structure or layout is also clear. If a capacitor has electrodes that are, say, “interdigitated” to provide high capacitance in a small area of an IC or lower impedance, what might this look like in a chip teardown? Are both electrodes in the same layer? How many fingers might be present in a minimal arrangement? How might the electrodes be placed in relation to other components? We almost certainly don’t want all these details in the claim, but we do want to paint a clear picture for the reader (who, let’s face it, more often than not is a layman at best) to be easily convinced that the images they will see from the chip teardown show the features of the claim.
The realities of drafting and prosecuting patent applications often require compromise. Details that become clear as a product is developed may not be available when a patent is prepared. Prior art may necessitate claim limitations that are less than ideal. However, keeping in mind at each stage the reality of what evidence might be available to demonstrate infringement will improve decisions and outcomes. Working with practitioners that understand this will help patentees secure optimum protection for their innovations.
If you would like to know more, please contact Peter Gray or another member of the Kilburn & Strode patents team.